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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 2 1 publication order number: mc34065 ? h/d mc34065?h, l mc33065?h, l high performance dual channel current mode controllers the mc34065 ? h,l series are high performance, fixed frequency, dual current mode controllers. they are specifically designed for off ? line and dc ? to ? dc converter applications offering the designer a cost effective solution with minimal external components. these integrated circuits feature a unique oscillator for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, drive output 2 enable pin, and two high current totem pole outputs ideally suited for driving power mosfets. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle ? by ? cycle current limiting, and a latch for single pulse metering of each output. these devices are available in dual ? in ? line and surface mount packages. the mc34065 ? h has uvlo thresholds of 14 v (on) and 10 v (off), ideally suited for off ? line converters. the mc34065 ? l is tailored for lower voltage applications having uvlo thresholds of 8.4 v (on) and 7.8 v (off). ? unique oscillator for precise duty cycle limit and frequency control ? current mode operation to 500 khz ? automatic feed forward compensation ? separate latching pwms for cycle ? by ? cycle current limiting ? internally trimmed reference with undervoltage lockout ? drive output 2 enable pin ? two high current totem pole outputs ? input undervoltage lockout with hysteresis ? low startup and operating current representative block diagram + ? + ? v ref sync input r t c t voltage feedback 1 compensation 1 drive output 2 enable voltage feedback 2 compensation 2 1 5 1 5 13 12 14 4 2 3 7 6 10 11 drive output 1 current sense 1 drive output 2 current sense 2 v cc 16 gnd 8 drive gnd 9 error amp 2 error amp 1 oscillator v ref undervoltage lockout 5.0v reference v cc undervoltage lockout latching pwm 1 latching pwm 2 r r http://onsemi.com semiconductor technical data high performance dual channel current mode controllers p suffix plastic package case 648 dw suffix plastic package case 751g (so ? 16l) 1 16 16 1 ordering information pin connections sync input c t r t voltage feedback 1 compensation 1 current sense 1 drive output 1 gnd v cc v ref drive output 2 enable voltage feedback 2 compensation 2 current sense 2 drive output 2 drive gnd 1 (top view) 2 3 4 5 6 7 89 11 10 12 13 14 15 16 t a = ? 40 to +85 c device operating temperature range package mc34065dw ? h t a = 0 to +70 c so ? 16l mc34065dw ? l mc34065p ? h mc34065p ? l mc33065dw ? h mc33065dw ? l mc33065p ? h mc33065p ? l plastic dip so ? 16l plastic dip
mc34065 ? h, l http://onsemi.com 2 maximum ratings rating symbol value unit power supply voltage v cc 20 v output current, source or sink (note 1) i o 400 ma output energy (capacitive load per cycle) w 5.0 j current sense, enable, and voltage feedback inputs v in ? 0.3 to +5.5 v sync input high state (voltage) low state (reverse current) v ih i il +5.5 ? 5.0 v ma error amp output sink current i o 10 ma power dissipation and thermal characteristics dw suffix, plastic package case 751g maximum power dissipation @ t a = 25 c thermal resistance, junction ? to ? air p suffix, plastic package case 648 maximum power dissipation @ t a = 25 c thermal resistance, junction ? to ? air p d r ja p d r ja 862 145 1.25 100 mw c/w mw c/w operating junction temperature t j +150 c operating ambient temperature (note 3) mc34065 mc33065 t a 0 to +70 ? 40 to +85 c storage temperature range t stg ? 65 to +150 c electrical characteristics (v cc = 15 v [note 2], r t = 8.2 k , c t = 3.3 nf, for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies to [note 3].) characteristics symbol min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = 25 c) v ref 4.85 5.0 5.13 v line regulation (v cc = 11 v to 20 v) reg line ? 2.0 20 mv load regulation (i o = 1.0 ma to 10 ma, v cc = 20 v) reg load ? 3.0 25 mv total output variation over line, load, and temperature v ref 4.8 ? 5.15 v output short circuit current i sc 30 100 ? ma oscillator and pwm sections total frequency variation over line and temperature v cc = 11 v to 20 v, t a = t low to t high mc34065 mc33065 f osc 46.5 45 49 49 51.5 53 khz frequency change with voltage (v cc = 11 v to 20 v) f osc / v ? 0.2 1.0 % duty cycle at each output maximum minimum dc max dc min 46 ? 49.5 ? 52 0 % sync input current high state (v in = 2.4 v) low state (v in = 0.8 v) i ih i il ? ? 170 80 250 160 a error amplifiers voltage feedback input (v o = 2.5 v) v fb 2.45 2.5 2.55 v input bias current (v fb = 5.0 v) i ib ? ? 0.1 ? 1.0 a open loop voltage gain (v o = 2.0 v to 4.0 v) a vol 65 100 ? db unity gain bandwidth (t j = 25 c) bw 0.7 1.0 ? mhz power supply rejection ratio (v cc = 11 v to 20 v) psrr 60 90 ? db
mc34065 ? h, l http://onsemi.com 3 error amplifiers output current source (v o = 3.0 v, v fb = 2.3 v) sink (v o = 1.2 v, v fb = 2.7 v) i source i sink 0.45 2.0 1.0 12 ? ? ma output voltage swing high state (r l = 15 k to ground, v fb = 2.3 v) low state (r l = 15 k to v ref , v fb = 2.7 v) v oh v ol 5.0 ? 6.2 0.8 ? 1.1 v
mc34065 ? h, l http://onsemi.com 4 electrical characteristics (v cc = 15 v [note 2], r t = 8.2 k , c t = 3.3 nf, for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies to [note 3].) characteristics symbol min typ max unit current sense section current sense input voltage gain (notes 4 and 5) a v 2.75 3.0 3.25 v/v maximum current sense input threshold (note 4) v th 0.9 1.0 1.1 v input bias current i ib ? ? 2.0 ? 10 a propagation delay (current sense input to output) t pln(in/out) ? 150 300 ns drive output 2 enable pin enable pin voltage ? high state (output 2 enabled) enable pin voltage ? low state (output 2 disabled) v ih v il 3.5 0 ? ? v ref 1.5 v low state input current (v il = 0 v) i ib 100 250 400 a drive outputs output voltage ? low state (i sink = 20 ma) output voltage ? low state (i sink = 200 ma) output voltage ? high state (i source = 20 ma) output voltage ? high state (i source = 200 ma) v ol v oh ? 1.6 12.8 10 0.3 2.4 13.3 11.2 0.5 3.0 ? 12.3 v output voltage with uvlo activated (v cc = 6.0 v, i sink = 1.0 ma) v ol(uvlo) ? 0.1 1.1 v output voltage rise time (c l = 1.0 nf) t r ? 50 150 ns output voltage fall time (c l = 1.0 nf) t f ? 50 150 ns undervoltage lockout section startup threshold (v cc increasing) ? l suffix ? h suffix v th 7.8 13 8.4 14 9.0 15 v minimum operating voltage after turn ? on (v cc decreasing) ? l suffix ? h suffix v cc(min) 7.2 9.0 7.8 10 8.4 11 v total device power supply current startup ? l suffix (v cc = 6.0 v) ? h suffix (v cc = 12 v) operating (note 2) i cc ? ? ? 0.4 0.6 20 0.8 1.0 25 ma notes: 1. maximum package power dissipation limits must be observed. notes: 2. adjust v cc above the startup threshold before setting to 15 v. notes: 3. low duty cycle pulse techniques are used during test to maintain junction notes: 3. temperature as close to ambient as possible: t low = 0 c for the mc34065 t high = +70 c for mc34065 t low = ? 40 c for the mc33065 t high = +85 c for mc33065 4. this parameter is measured at the latch trip point with v fb = 0 v 5. comparator gain is defined as av = v compensation v current sense
mc34065 ? h, l http://onsemi.com 5 figure 1. timing resistor versus oscillator frequency figure 2. maximum output duty cycle versus oscillator frequency 4.0 6.0 8.0 10 14 16 r t , timing resistor (k ) f osc, oscillator frequency (hz) 12 3.3nf 500pf 220pf 330pf 2.2nf 5.0nf 1.0nf 10k 30k 50k 300k 500k 100k 1.0 m 100pf dc max , duty cycle maximum (%) f osc, oscillator frequency (hz) 38 40 42 44 48 50 46 output2 output1 10k 30k 50k 300k 500k 100k 1.0 m v cc =15v r t =4.0 k to 16k t a = 25 c l =15pf c t = 10nf v cc =15v t a =25 c
mc34065 ? h, l http://onsemi.com 6 figure 3. error amp small ? signal transient response figure 4. error amp large ? signal transient response figure 5. error amp open loop gain and phase versus frequency figure 6. current sense input threshold versus error amp output voltage 1.0 s/div 20 mv/div 1.0 s/div 200 mv / div f, frequency (hz) a vol , open loop voltage gain (db) , excess phase (degrees) 10 100 1.0 k 10 k 100 k 1.0 m 10 m 0 30 60 90 120 150 180 phase gain v cc =15v v o =1.5 v to 2.5v r l =100 k t a =25 c 0 1.0 2.0 3.0 4.0 7.0 5.0 6.0 v o , error amp output voltage (v) v th , current sense input threshold (v) v cc =15v a v =?1.0 t a =25 c v cc =15v a v =?1.0 t a =25 c figure 7. reference voltage change versus source current figure 8. reference short circuit current versus temperature v ref , reference voltage change (mv) i ref , reference source current (ma) 0 20 40 60 80 100 120 i sc , reference short circuit current (ma) t a , ambient temperature ( c) ?55 ?25 0 25 50 75 100 125 v cc =15v r l 0.1 2.55v 2.50v 2.45v 3.0v 2.50v 2.0v 100 80 60 40 20 0 ?20 0.6 1.2 1.0 0.2 0.4 0.8 0 0 ?4.0 ?8.0 ?12 ?16 ?20 ?24 120 100 80 60 v cc = 15 v t a = 125 c t a = 25 c t a = ?55 c v cc = 15 v t a = ?55 c t a = 25 c t a = 125 c
mc34065 ? h, l http://onsemi.com 7 v cc =15v c l =15pf t a =25 c v cc =15v c l =1.0nf t a =25 c v cc =11 v to 15v t a =25 c figure 9. reference load regulation figure 10. reference line regulation figure 11. output saturation voltage versus load current figure 12. output waveform v o , output voltage change (2.0 mv/div) 1.0 ms/div 1.0 ms/div v o , output voltage change (2.0 mv/div) v sat , output saturation voltage (v) i o , output load current (ma) 0 ?2.0 ?4.0 ?6.0 4.0 2.0 0 0 100 200 300 400 v cc t a =?55 c gnd sink saturation (load to v cc ) source saturation (load to ground) t a =25 c t a =?55 c t a =25 c v cc =15v 80 s pulsed load 120 hz rate 90% ? 10% ? 100 ns/div v cc =15v i o =1.0 ma to 10ma t a =25 c figure 13. output cross conduction current figure 14. supply current versus supply voltage v o2 , output voltage 2; v o1 , output voltage 1 i cc , supply current 10 v/div 50 ma/div 10 v/div 100 ns/div i cc , supply current (ma) 32 24 16 8.0 0 0 4.0 8.0 12 16 20 v cc , supply voltage (v) ?h suffix ?l suffix r t =10k c t =3.3nf v fb =0v current sense=0v t a =25 c
mc34065 ? h, l http://onsemi.com 8 operating description the mc34065 ? h,l series are high performance, fixed frequency, dual channel current mode controllers specifically designed for off ? line and dc ? to ? dc converter applications. these devices offer the designer a cost effective solution with minimal external components where independent regulation of two power converters is required. the representative block diagram is shown in figure 15. each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. the oscillator, reference regulator, and undervoltage lock ? out circuits are common to both channels. oscillator the unique oscillator configuration employed features precise frequency and duty cycle control. the frequency is programmed by the values selected for the timing components r t and c t . capacitor c t is charged and discharged by an equal magnitude internal current source and sink, generating a symmetrical 50 percent duty cycle waveform at pin 2. the oscillator peak and valley thresholds are 3.5 v and 1.6 v respectively. the source/sink current magnitude is controlled by resistor r t . for proper operation over temperature it must be in the range of 4.0 k to 16 k as shown in figure 1. as c t charges and discharges, an internal blanking pulse is generated that alternately drives the center inputs of the upper and lower nor gates high. this, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non ? overlapping output duty cycles. output 2 is enabled while c t is charging, and output 1 is enabled during the discharge. figure 2 shows the maximum output duty cycle versus oscillator frequency. note that even at 500 khz, each output is capable of approximately 44% on ? time, making this controller suitable for high frequency power conversion applications. in many noise sensitive applications it may be desirable to frequency ? lock the converter to an external system clock. this can be accomplished by applying a clock signal as shown in figure 17. for reliable locking, the free ? running oscillator frequency should be set about 10% less than the clock frequency. referring to the timing diagram shown in figure 16, the rising edge of the clock signal applied to the sync input, terminates charging of c t and drive output 2 conduction. by tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. a circuit method for this, and multi ? unit synchronization, is shown in figure 18. error amplifier each channel contains a fully ? compensated error amplifier with access to the inverting input and output. the amplifier features a typical dc voltage gain of 100 db, and a unity gain bandwidth of 1.0 mhz with 71 of phase margin (figure 5). the noninverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. the maximum input bias current is ? 1.0 a which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 5, 12) is provided for external loop compensation. the output voltage is offset by two diode drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no pulses appear at the drive output (pin 7, 10) when the error amplifier output is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a soft ? start interval (figures 20, 21). the minimum allowable error amp feedback resistance is limited by the amplifier?s source current (0.5 ma) and the output voltage (v oh ) required to reach the comparator?s 1.0 v clamp level with the inverting input at ground. this condition happens during initial system startup or when the sensed output is shorted: r f(min) 3.0 (1.0 v) 1.4 v 0.5 ma = 8800 current sense comparator and pwm latch the mc34065 operates as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output. thus the error signal controls the peak inductor current on a cycle ? by ? cycle basis. the current sense comparator ? pwm latch configuration used ensures that only a single pulse appears at the drive output during any given oscillator cycle. the inductor current is converted to a voltage by inserting a ground ? referenced sense resistor r s in series with the source of output switch q1. this voltage is monitor ed by the current sense input (pin 6, 11) and compared to a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 5, 12 where: i pk = v (pin 5, 12) ? 1.4 v 3 r s abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. under these conditions, the current sense comparator threshold will be internally clamped to 1.0 v. therefore the maximum peak switch current is: i pk(max) = 1.0 v r s
mc34065 ? h, l http://onsemi.com 9 when designing a high power switching regulator it may be desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 19. the two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive reduction of the i pk(max) clamp voltage. a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and output rectifier recovery time. the addition of an rc filter on the current sense input with a time constant that approximates the spike duration will usually eliminate the instability, refer to figure 24. undervoltage lockout two undervoltage lockout comparators have been incorporated to guarantee that the ic is fully functional before the output stages are enabled. the positive power supply terminal (v cc ) and the reference output (v ref ) are each monitored by separate comparators. each has built ? in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the v cc comparator upper and lower thresholds are 14 v/10 v for ? h suffix, and 8.4 v/7.6 v for ? l suffix. the v ref comparator upper and lower thresholds are 3.6 v/3.4 v respectively. the large hysteresis and low startup current of the ? h suffix version makes it ideally suited in off ? line converter applications where efficient bootstrap startup techniques are required (figure 28). the ? l suffix version is intended for lower voltage dc ? to ? dc converter applications. the minimum operating voltage for the ? h suffix is 11 v and 8.2 v for the ? l suffix. drive outputs and drive ground each section contains a single totem ? pole output stage that is specifically designed for direct drive of power mosfets. the drive outputs are capable of up to 400 ma peak current with a typical rise and fall time of 50 ns with a 1.0 nf load. additional internal circuitry has been added to keep the outputs in a sinking mode whenever an undervoltage lockout is active. this characteristic eliminates the need for an external pull ? down resistor. the totem ? pole output has been optimized to minimize cross ? conduction current in high speed operation. the addition of two 10 resistors, one in series with the source output transistor and one in series with the sink output transistor, reduces the cross ? conduction current to minimal levels, as shown in figure 13. although the drive outputs were optimized for mosfets, they can easily supply the negative base current required by bipolar npn transistors for enhanced turn ? off (figure 25).
mc34065 ? h, l http://onsemi.com 10 figure 15. representative block diagram + ? ? + ? + + ? + ? ? + ? + 12 13 14 5 4 2 3 1 15 7 6 10 11 v ref sync input r t c t voltage feedback 1 compensation 1 enable input voltage feedback 2 compensation 2 v in =15v v cc 16 q2 r s current sense 2 drive output 2 current sense 1 drive output 1 r s q1 10 10 10 10 gnd 8 drive gnd 9 = sink only positive true logic 1.0v r s q r r pwm latch 2 s r q current sense comparator 2 2r error amp 2 error amp 1 v ref 250 a 1.0ma 1.0v r 1.0ma oscillator 3.6v + ? 20k internal bias reference regulator r r 2.5v pwm latch 1 v cc uvlo + ? current sense comparator 1 v ref uvlo 2r
mc34065 ? h, l http://onsemi.com 11 figure 16. timing diagram sync input capacitor c t latch 1 set" input compensation 1 current sense 1 latch 1 reset" input drive output 1 drive output 2 enable latch 2 set" input compensation 2 current sense 2 drive output 2 latch 2 reset" input the outputs do not contain internal current limiting, therefore an external series resistor may be required to prevent the peak output current from exceeding the 400 ma maximum rating. the sink saturation (v ol ) is less than 0.75 v at 50 ma. a separate drive ground pin is provided and, with proper implementation, will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when reducing the i pk(max) clamp level. figure 23 shows the proper ground connections required for current sensing power mosfet applications. drive output 2 enable pin this input is used to enable drive output 2. drive output 1 can be used to control circuitry that must run continuously such as volatile memory and the system clock, or a remote controlled receiver, while drive output 2 controls the high power circuitry that is occasionally turned off. reference the 5.0 v bandgap reference is trimmed to 2.0% tolerance at t j = 25 c. the reference has short circuit protection and is capable of providing in excess of 30 ma for powering any additional control system circuitry. design considerations do not attempt to construct the converter on wire ? wrap or plug ? in prototype boards. high frequency circuit layout techniques are imperative to prevent pulse ? width jitter. this is usually caused by ex cessive noise pick ? up imposed on the current sense or v oltage feedback inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v cc and v ref may be required depending upon circuit layout. this provides a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage ? divider should be located close to the ic and as far as possible from the power switch and other noise generating components.
mc34065 ? h, l http://onsemi.com 12 figure 17. external clock synchronization figure 18. external duty cycle clamp and multi ? unit synchronization ? + r 220p f r t r r 1 5 1 3 2 4 5 c t external sync input bias osc . 20k ea1 1.0v 2r the external diode clamp is required if the negative sync current is greater than ? 5.0 ma. ? + ? + ? + 6 5 2 c r b mc1455 r s q 3 7 4 8 r a v ref 15 1 3 2 4 5 to additional mc34065s 2r r 1.0v osc. bias r r 5.0k 5.0k 5.0k 1 ea1 f = 1.08 (r a + r b )c d max drive output 1 = r b r a + r b d max drive output 2 = r a r a + r b 20k pin function description pin function description 1 sync input a narrow rectangular waveform applied to this input will synchronize the oscillator. a dc voltage within the range of 2.4 v to 5.5 v will inhibit the oscillator. 2 c t timing capacitor c t connects from this pin to ground setting the free ? running oscillator frequency range. 3 r t resistor r t connects from this pin to ground precisely setting the charge current for c t . r t must be between 4.0 k and 16 k. 4 voltage feedback 1 this pin is the inverting input of error amplifier 1. it is normally connected to the switching power supply output through a resistor divider. 5 compensation 1 this pin is the output of error amplifier 1 and is made available for loop compensation. 6 current sense 1 a voltage proportional to the inductor current is connected to this input. pwm 1 uses this information to terminate conduction of output switch q1. 7 drive output 1 this pin directly drives the gate of a power mosfet q1. peak currents up to 400 ma are sourced and sunk by this pin. 8 gnd this pin is the control circuitry ground return and is connected back to the source ground. 9 drive gnd this pin is a separate power ground return that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 10 drive output 2 this pin directly drives the gate of a power mosfet q2. peak currents up to 400 ma are sourced and sunk by this pin. 11 current sense 2 a voltage proportional to inductor current is connected to this input. pwm 2 uses this information to terminate conduction of output switch q2. 12 compensation 2 this pin is the output of error amplifier 2 and is made available for loop compensation. 13 voltage feedback 2 this pin is the inverting input of error amplifier 2. it is normally connected to the switching power supply output through a resistor divider. 14 drive output 2 enable a logic low at this input disables drive output 2. 15 v ref this is the 5.0 v reference output. it can provide bias for any additional system circuitry. 16 v cc this pin is the positive supply of the control ic. the minimum operating voltage range after startup is 11 v to 15.5 v for the ? h suffix, 8.2 v to 9.5 v for the ? l suffix.
mc34065 ? h, l http://onsemi.com 13 figure 19. adjustable reduction of clamp level figure 20. soft ? start circuit figure 21. adjustable reduction of clamp level with soft ? start figure 22. mosfet parasitic oscillations figure 23. current sensing power mosfet figure 24. current waveform spike suppression ? + + ? ? + v ref 1 5 1 3 2 4 5 r 1 r 2 ea1 r r bias 5.0v ref osc. s r q + 20k v cc v in q1 r s 6 7 16 v clamp 1.0ma 2r r 1.0v pwm latch 1 + v clamp 1.67 r 2 r 1 1 + 0.33 x 10 ?3 (r 1 ) i pk(max) v clamp r s where: 0 v clamp 1.0 v _ _ ? + ? + bias osc. 1.0ma 1.0m c 15 1 3 2 4 ea1 r 1.0v 20k r r v ref t soft?start 2100 c in f 5 2r c r 1 r 2 r 1 r 2 ? + ? + ? + v in v cc 16 + + q1 r s 6 7 5.0v ref 20k bias r r v ref 15 1 3 2 4 5 mpsa63 r 1 r 2 c ea1 2r 1.0v r v clamp pwm latch 1 s r q i pk(max) v clamp r s r 2 r 1 1 v clamp 1.67 where: 0 v clamp 1.0 v t soft?start = in osc _ _ ? + 1 1 ? v c 3 v clamp series gate resistor r g may be needed to damp high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate ? source circuit. r g will decrease the mosfet switching speed. schottky diode d 1 is required if circuit ringing drives the output pin below ground. ? + ? + + ? v cc 16 + 5.0v ref + pwm latch 1 q s r 1n5819 r g q1 r s 7 6 v in d 1 _ ? virtually lossless current sensing can be achieved with the implementation of a sensefet power switch. for proper operation during over current conditions, a reduction of the i pk(max) clamp level must be implemented. refer to figures 19 and 21. _ + _ + + + ? s r q v cc v in 5.0v ref pwm latch 1 7 6 r s 1/4w d s k m g sensefet power ground to input source return drive ground to pin 9 control circuitry ground to pin 8 if: sensefet = mtp10n10m r s = 200 then: v pin6 = 0.075 i pk v pin6 + _ _ 16 r dm(on) + r s r s i pk r ds(on) the addition of the rc filter will eliminate instability caused by the leading edge spike on the current waveform. _ + + _ + + _ _ v in q1 r s + ? 5.0v ref s r q pwm latch 1 v cc 7 6 16 c r
mc34065 ? h, l http://onsemi.com 14 figure 25. bipolar transistor drive figure 26. isolated mosfet drive figure 27. dual charge pump converter the totem ? pole outputs can furnish negative base current for enhanced transistor turn ? off, with the addition of capacitor c 1 . i b + ? 0 base charge removal v in c 1 r s ? + q1 + _ + ? ? + + ? 5.0v ref s r q v cc v in 16 pwm latch 1 7 6 d 1 n p n s c r isolation boundary i pk v (pin 6) 1.4 3r s n p n s the capacitor?s equivalent series resistance must limit the drive output current to 400 ma. an additional series resistor may b e required when using tantalum or other low esr capacitors. the positive output can provide excellent line and load regulation by connecting th e r 2 /r 1 resistor divider as shown. output load regulation i o (ma) +v o (v) ? v o (v) 0 1.0 5.0 10 50 28.43 27.72 27.04 26.20 20.52 ? 13.89 ? 12.90 ? 12.25 ? 11.44 ? 5.80 ? + + _ + _ ? + + ? ? + + ? ? + + + + + 15 1 3 2 4 5 14 13 12 1.0nf 12k 2.5v r r bias osc. 5.0v ref 20k 1.0ma 1.0ma r 2r 1.0v ea2 89 s r r q pwm latch 2 s q r pwm latch 1 r 16 v cc =15v + 47 27 10 7 47 6 10 11 47 r 2 r 1 +v o 2.0v cc ?v o ?v cc 1n5819 1n5819 2r 250 a 10 10 10 10 27 10 connect to pin 4 for closed?loop regulation. v o 2.5 r 2 r 1 1 ea1 1.0v
mc34065 ? h, l http://onsemi.com 15 figure 28. 125 watt off ? line converter tes - t condi- tions re- sults line regulation 100 v output 12 v outputs 9.0 v output efficien- cy v in = 92 vac to 138 vac i o = 1.0 a i o = 1.0 a i o = 0.1 a v in = 115 vac i o = 0.25 a to 1.0 a i o = 0.25 a to 1.0 a i o = 0.08 a to 0.1 a v in = 115 vac i o = 1.0 a i o = 1.0 a i o = 0.1 a v in = 115 vac, r l = 0.1 vin = 115 vac, po = 125 w = 40 mv or 0.02% = 32 mv or 0.13% = 55 mv or 0.31% = 50 mv or 0.025% = 320 mv or 1.2% = 234 mv or 1.3% 40 mvpp 100 mvpp 60 mvpp 4.3 a 17 a output hiccups 86 % t1 ? t2 ? t3 ? l1, l3, l4 ? l2 ? 468 h per section at 2.5 a, coilcraft e3496a. primary: 156 turns, #34 awg primary feedback: 19 turns, #34 awg secondary: 17 turns, #28 awg core: tdk pc30 ee22 ? z bobbin: be22 ? 118cp gap: 0.001 for a primary inductance of 6.8 mh primary: 56 turns, #23 awg (2 strands) bifiliar wound secondary: 12 v, 4 turns, #23 awg (4 strands) quadfiliar wound secondary 100 v: 32 turns, #23 awg (2 strands) bifiliar wound core: tdk pc30 eer40 g0.76 bobbin: beer40 ? 1112cp gap: 0.030 for a primary 25 h at 1.0 a, coilcraft z7157. 10 h at 3.0 a, coilcraft pcv ? 0 ? 010 ? 03. load regulation 100 v output 12 v outputs 9.0 v output output ripple 100 v output 12 v outputs 9.0 v output short circuit current 100 v output 12 v outputs 9.0 v output inductance of 212 h ? + + _ ? + + _ + ? + ? ? + 9 8 ? + t 10 cold <1 hot 92vac to 138vac 0.22 t1 mda 970g5 + 270 56k 75k 16.2k 4.7k 47k 47k 1/2 4n35 1.0m 100 pf 4.7 nf 5.6k 15 1 3 2 4 5 14 13 12 ea2 2r 1.0v r 1.0v 2r r osc. 20k bias r r 3.0a 5.0v ref 16 10 10 10 10 pwm latch 2 s r r q pwm latch 1 r s q mc34065?h 470pf 1.0k 22 10 11 6 7 mtd 2n50 1.0 k 470 pf 3.3 1n 4937 3300 pf 12k 22 330 pf 10k 220 100 + + mur110 t2 l1 l3 l4 t3 l2 1n4148 330 330 10 10 10 100 1.3k 51k 68k 0.01 3.3k 0.01 tl 43a 10k 0.001 100 mur 440 mur415 10 0.001 mur415 1000 1000 + + 1/2 4n35 9.0v 0.1a rtn 12v 1.0a rtn ?12v 1.0a 100v 1.0a rtn 180 pf ea1 0.082 mth 8n45 mps a20 + output 2 shutdown + + + + mur110 0.05
mc34065 ? h, l http://onsemi.com 16 4 1/2 figure 29. pc board circuit side and component view 5 11/16 (circuit view) ac input 9v 100v 12v ?12v (component view) * *100 v and 12 v shutdown
mc34065 ? h, l http://onsemi.com 17 outline dimensions p suffix plastic package case 648 ? 08 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 dw suffix plastic package case 751g ? 03 (sop ? 8+8l) issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc34065 ? h, l http://onsemi.com 18 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc34065 ? h/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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